1. Field of the Invention
The present invention relates to buffer circuitry fabricated on semiconductor dies, and more particularly to buffering circuitry located in the signal line routing regions or channels of integrated circuits.
2. Description of the Related Art
Integrated circuits have become key components of many consumer and commercial electronic products, often replacing discrete components and enhancing product functionality. The semiconductor processing technologies that produce these integrated circuits have advanced to the point where complete systems can now be reduced to a single integrated circuit or application specific integrated circuit (ASIC) device. These integrated circuits (also referred to as "chips") may incorporate many functions that previously could not be implemented together on a single chip, including: microprocessors, digital signal processors, communication circuits, mixed signal and analog functions, large blocks of memory and high speed interfaces. The requisite level of integration, however, significantly complicates the design and manufacturing processes.
One difficult task facing integrated circuit manufacturers involves interconnecting the millions of logic gates and megabytes of memory that may be present on a chip. To aid in this task, new metallization schemes have been developed that allow five or more distinct "levels" or layers of metal interconnect wires, with pitches of 0.5 .mu.m and tighter on the first few layers. In most multiple layer metallization schemes, the various metal interconnect wires have different nominal widths and heights, different distances from transistor gates, and are insulated by oxide layers of varying thickness.
As semiconductor processes migrate further into the deep sub-micron range with multiple metal layers, increased circuit speeds allow the delay caused by the metal interconnect wires to reach the magnitude of active elements. The performance of sub-micron integrated circuitry can be dominated by propagation delays through the metal interconnect wires rather than the basic gate delays (i.e., transistor delays) of individual logic elements (also referred to as "logic cells" or "cells"). This phenomenon is attributable to a number of factors, including the fact that as the width of a wire shrinks in deep sub-micron designs, the resistance of the wire increases. Further, as transistor features shrink, their drive capability also decreases. It has been estimated that interconnect contributes as much as 70-80% of the total delay in integrated circuits implemented in 0.25 .mu.m process rules.
The aforementioned delays are manifested by "ramp time" effects. When a logic gate asserts or desserts a signal by applying or removing a voltage at one end of a signal line, the voltage at the input to a logic gate receiving the signal does not change instantaneously. Instead, there is a ramp time delay due principally to signal line impedance and capacitance. The voltage at the other end of the signal line "ramps" to the applied voltage, in a continuous, but not instantaneous, manner. Consequently, when a logic gate in one part of an integrated circuit sends a signal to a logic gate in another part of the integrated circuit, a small but noticeable propagation delay and "ramp" time is realized while the signal travels along a signal line. The propagation delay can be conceptualized as the delay between the time a signal transition is initiated and the time the signal begins ramping to an applied voltage.
An increase in average signal ramp times and propagation delays frequently results in a greater number of critical timing paths (e.g., signal paths in which best or worst case simulated propagation delays may approach the limits required for proper functionality). Many timing problems involve such critical timing paths, which effectively limit clock frequencies. Further, faster input signal ramp times may produce different results at a logic cell's output than slower input signal ramp times. For these reasons, errors due to signal ramp times and/or propagation delays become a greater concern in sub-micron integrated circuit designs.
When performing timing analysis on an integrated circuit design, typical verification and synthesis tools estimate signal timing using floorplan or layout-based delay information supplied via back-annotation. For example, synthesis and floorplanning tools are commonly used to identify critical timing paths, while layout parasitic extraction (LPE) tools in conjunction with proprietary technology libraries are used to estimate the delay each critical path will experience in final layout. In the interest of improving manufacturing yields, functional simulations are often performed using these estimated delay values to verify operability. The terms "floorplan" and "layout" refer to the physical geometry of an integrated circuit or die. A floorplan consists of placed groupings of integrated circuit elements, including logic cells, that are used by signal wire routing tools in placing and functionally interconnecting the elements. A layout includes the completed integrated circuit design and is represented by a layout database containing information for generating the masks used to fabricate integrated circuits.
Within the core logic region of a typical integrated circuit, most of the digital logic cells are located in groupings of cells aligned in rows. These "cell rows" are separated by signal line routing channels in which the metal interconnect lines are disposed. Within each cell row, the individual logic cells are tightly grouped in order to conserve expensive silicon area and reduce the length of the signal lines. Layout tools place related logic gates as closely as practical, but signals must sometimes traverse relatively lengthy signal lines.
To correct resulting timing faults, a system designer can utilize buffering circuitry along failing critical paths to meet timing requirements. The "buffer" cells are logic cells which amplify a weak signal and can reduce ramp time on lengthy signal lines or heavily loaded signal lines. In large integrated circuits requiring many buffer cells, however, total die size is often negatively impacted due to the fact that the buffer cells themselves are included in and increase the size of the cell rows.